This invention relates to CMOS semiconductor devices operating with a low voltage power supply and a high rated voltage. This invention relates to semiconductor integrated circuits for formation of a CPU or the like, and in more particular to semiconductor devices for use in logic circuits or drive circuits suitable for high voltage drive.
A cross-section of one prior art high rated voltage inverter circuit with CMOS structure is shown in FIG. 2. An N well 2 is provided in the surface of a P type silicon substrate 1. Provided in the surface of the N well is a high rated voltage P type insulated gate field effect transistor (referred to as "HVPMOSFET" hereinafter). A high rated voltage insulated gate field effect transistor (HVNMOSFET) is provided in the surface of the P type substrate 1. The HVPMOSFET has a drain region which consists of a lightly doped drain region 21C and a heavily doped drain region 21D within it in order to attain an increased withstanding voltage. A source region also consists of a lightly doped source region 21 and a heavily doped source region 21A as needed. Likewise, a source region of the HVNMOSFET consists of a lightly doped source region 22B and a heavily doped source region 22A, while a drain thereof consists of a lightly doped drain region drain 22C and a heavily doped drain region 22D. Gate electrodes 21F, 22F overlie the substrate with gate insulation films 21E, 22E being provided therebetween respectively. While not shown in the drawing, a low rated voltage P type insulated gate field effect transistor (LVPMOSFET) and a low rated voltage N type insulated gate field effect transistor (LVNMOSFET) are formed in the surface of the same substrate. Since there is no need for drain regions of the LVNMOSFET and LVPMOSFET to exhibit high rated voltage, these are formed of heavily doped drain regions only.
FIG. 3 is a cross-sectional view of a typical prior art insulated gate field effect transistor (referred to as "MISFET" hereinafter). In the case of an N type MISFET as an example, an N type source region 102 and a drain region 103 spaced apart from each other are provided in the surface of a P type silicon substrate 101, while a gate electrode 122 is provided to overlie a channel formation region consisting of a substrate portion defined between the source region 102 and drain region 103 with a gate oxide film 121 being sandwiched therebetween. Upon application of a positive voltage at the gate electrode 122 relative to the source region 102, the channel formation region is inverted in conductivity from P type to N type causing a drain current to flow between the source region 102 and the drain region 103. This enables the gate electrode 122 to control the impedance between the source region 102 and the drain region 103. When a high voltage higher than the power supply voltage is applied to the gate electrode 122, the high voltage is also applied to the gate oxide film 121. Accordingly, as shown in FIG. 3, in a MISFET being applied with such high voltage, a gate insulation film is provided which is greater in thickness than a MISFET operating with a low potential gate voltage.
However, in the prior art semiconductor device, since almost entire voltage applied as the gate voltage is applied to the gate insulation film, there are problems that follow.
(1) It is difficult to make thinner the gate insulation film with respect to the gate voltage.
(2) When the high rated voltage MISFET and low rated voltage MISFET are formed together on the same substrate, it is required that an individual gate insulation film be provided for each MISFET.
Further, in the prior art semiconductor device, there is a problem in that the manufacturing cost thereof remains higher due to additional formation of lightly doped drain regions of HVPMOSFET and HVNMOSFET.
It is therefore an object of the present invention to obtain a semiconductor device of simple structure and low cost which does not require any new, additional manufacturing steps of forming lightly doped drain regions, enables gate insulation films to be made thinner, and also avoids the use of a plurality of gate insulation films.